1. Field of Invention
The present invention relates to a method for manufacturing metal-oxide-semiconductor (MOS) transistor. More particularly, the present invention relates to a MOS transistor having a local pocket structure that can be used for fabricating embedded memory.
2. Description of Related Art
Logic circuit devices and memory devices are normally formed on separate silicon chips. However, as a faster operating speed is demanded, the newer generation of integrated circuit chips is likely to have a mixture of these two types of devices in a single chip. For example, embedded dynamic random access memory (DRAM) has a chip layout that includes a mixture of logic circuit devices and memory devices.
Nevertheless, logic circuit devices and memory devices have different functional properties that require different processing operations. Logic circuit devices are mainly used for logic computation, and therefore should have a very high data-transmission rate. Hence, the source/drain regions of a logic device must have a high concentration of dopants. In addition, the source/drain regions must have a low sheet resistance. Consequently, a layer of metal silicide is generally deposited over the upper surface of a source/drain terminal. In contrast, memory devices are used mainly for data storage. Because a correct data bit can be registered within a memory unit for a defined period only if leakage current is small, a lightly doped source/drain terminal is usually required. Hence, a metal silicide layer is rarely formed over the source/drain terminal of a memory transistor.
As the line width of a device continues to shrink, a short channel effect becomes a critical factor affecting the operational characteristics of the device. To prevent further deterioration of the device, the diffusion of dopants between the source/drain terminals of a MOS transistor in the logic circuit area must be prevented. The conventional method of preventing dopant diffusion includes doping the substrate surrounding the source/drain terminal with dopants having a polarity opposite to the dopants in the source/drain terminal itself. In other words, doped pocket structures are formed around the source/drain terminals. However, forming a doped pocket structure around the source/drain terminal leads to some other problems. For example, the source/drain region and the pocket structure together produce a rather large PN junction capacitance. Furthermore, a portion of the doped pocket structure may overlap with the inversion region. Hence, more intense short-channel inversion effects result, leading to a reduction of device current and a lowering of device efficiency.
In light of the foregoing, there is a need to provide an improved method for manufacturing a MOS transistor.